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ADV7195
PROGRESSIVE SCAN MODE
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Figure 16 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
Output Standard Selection (MR00–MR01)
These bits are used to select the output levels for the ADV7195.
If EIA-770.2 (MR01–00 = “00”) is selected, the output levels
will be: 0 mV for blanking level, 700 mV for peak white for the Y
channel, ± 350 mV for Pr, Pb outputs and –300 mV for Sync.
Sync insertion on the Pr, Pb channels is optional.
If EIA-770.1 (MR01–00 = “01”) is selected, the output levels
will be: 0 mV for blanking level, 714 mV for peak white for the Y
channel, ± 350 mV for Pr, Pb outputs and –286 mV for Sync.
Optional sync insertion on the Pr, Pb channels is not possible.
If Full I/P Range (MR01–00 = “10”) is selected, the output
levels will be: 0 mV for blanking level, 700 mV for peak white for
the Y channel, ± 350 mV for Pr, Pb outputs and –300 mV for
Sync. Sync insertion on the Pr, Pb channels is optional. This
mode is used for RS-170, RS-343A standard output compatibil-
ity. Refer to Figures 61 to 64 for output level plots.
Input Control Signals (MR02–MR03)
These control bits are used to select whether data is input with
external horizontal, vertical and blanking sync signals or if the
data is input with embedded EAV/SAV codes.
An Asynchronous timing mode is also available using TSYNC,
SYNC and DV as input control signals. These control signals
have to be programmed by the user.
Figure 17 shows an example of how to program the ADV7195
to accept a different high definition standard but SMPTE293M,
SMPTE274M, SMPTE296M or ITU-R.BT1358 standard.
Input Standard (MR04)
Select between 525p progressive scan input or 625p progressive
scan input.
Reserved (MR05)
A “0” must be written to this bit.
DV Polarity (MR06)
This control bit allows the user to select the polarity of the DV
input control signal to be either active high or active low. This is
in order to facilitate interfacing from I to P Converters which
use an active low blanking signal output.
Reserved (MR07)
A “0” must be written to this bit.
MR07
MR06
MR05
MR04
MR03
MR02
MR01
MR00
MR07
ZERO MUST
BE WRITTEN
MR05
ZERO MUST
BE WRITTEN
INPUT
STANDARD
MR04
INPUT CONTROL SIGNALS
MR03 MR02
TO THIS BIT
TO THIS BIT
0 525P
1 625P
0
0
0
1
HSYNC / VSYNC /DV
EAV/SAV
DV POLARITY
MR06
0 ACTIVE HIGH
1 ACTIVE LOW
1
1
0
1
TSYNC/ SYNC /DV
RESERVED
OUTPUT STANDARD SELECTION
MR01 MR00
Figure 16. Mode Register 0
–14 –
0
0
1
1
0
1
0
1
EIA-770.2
EIA-770.1
FULL I/P RANGE
RESERVED
REV. A
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